参数资料
| 型号： | ST16C2552IJ44TR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 5/34页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B DUAL 44PLCC |
| 标准包装： | 500 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 3.3 V ~ 5 V |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
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ST16C2552
13
REV. 4.2.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
FIGURE 10. RECEIVER OPERATION IN FIFO MODE
Receive Data Shift
Register (RSR)
RXFI
16X Clock
E
rro
rT
ags
(1
6-se
ts)
E
rro
rTa
gs
in
LS
R
bi
ts
4:
2
16 bytes by 11-bit
wide FIFO
Receive Data Characters
Data Bit
Validation
RX FIFO
RHR
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
FIFO is Enabled by FCR bit-0=1
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