- 您现在的位置：买卖IC网 > PDF目录11832 > ST16C454IJ68-F (Exar Corporation)IC UART QUAD 68PLCC PDF资料下载
参数资料
| 型号： | ST16C454IJ68-F |
| 厂商： | Exar Corporation |
| 文件页数： | 8/29页 |
| 文件大小： | 0K |
| 描述： | IC UART QUAD 68PLCC |
| 标准包装： | 19 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 1 字节 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC |
| 包装： | 管件 |
| 其它名称： | 1016-1565-5 ST16C454IJ68-F-ND |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
ST16C454
16
Rev. 3.31
Table 7, INTERRUPT SOURCE TABLE
Priority
[ ISR BITS ]
Source of the interrupt
Level
Bit-3 Bit-2 Bit-1 Bit-0
1
0110
LSR (Receiver Line Status Register)
2
0100
RXRDY (Received Data Ready)
3
0010
TXRDY ( Transmitter Holding Register Empty)
4
0000
MSR (Modem Status Register)
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (See Interrupt Source
Table).
ISR BIT 4-7:
Not used - Initialized to a logic 0.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
Word length
00
5
01
6
10
7
11
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in conjunc-
tion with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
5,6,7,8
1
5
1-1/2
1
6,7,8
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
相关PDF资料 |
PDF描述 |
|---|---|
| VE-25D-IY | CONVERTER MOD DC/DC 85V 50W |
| ST16C654CQ64TR-F | IC UART FIFO 64B QUAD 64LQFP |
| XR16V564IV80-F | IC UART FIFO 32B QUAD 80LQFP |
| VE-25B-IY | CONVERTER MOD DC/DC 95V 50W |
| XR16M564IV80-F | IC UART FIFO 32B QUAD 80LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C454IJ68TR-F | 功能描述:UART 接口集成电路 QUAD UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C550 | 制造商:EXAR 制造商全称:EXAR 功能描述:UART WITH 16-BYTE FIFO’s |
| ST16C550_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:UART WITH 16-BYTE FIFO’s |
| ST16C550CJ44 | 制造商:Exar 功能描述:Bulk |
| ST16C550CJ44-F | 功能描述:UART 接口集成电路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。