参数资料
型号: ST16C654CQ64TR-F
厂商: Exar Corporation
文件页数: 1/51页
文件大小: 0K
描述: IC UART FIFO 64B QUAD 64LQFP
标准包装: 1,000
特点: *
通道数: 4,QUART
FIFO's: 64 字节
规程: RS232
电源电压: 2.97 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
AUGUST 2005
REV. 5.0.2
GENERAL DESCRIPTION
The ST16C654/654D1 (654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, transmit and receive FIFO trigger levels,
automatic hardware and software flow control, and
data rates of up to 1.5 Mbps. Each UART has a set
of registers that provide the user with operating status
and control, receiver error indications, and modem
serial interface controls. Selectable interrupt polarity
provides flexibility to meet design requirements. An
internal
loopback
capability
allows
onboard
diagnostics. The 654 is available in 64 pin LQFP, 68
pin PLCC and 100 pin QFP packages. The 64 pin
package only offers the 16 mode interface, but the 68
and 100 pin packages offer an additional 68 mode
interface which allows easy integration with Motorola
processors.
The ST16C654CQ64 (64 pin) offers
three
state
interrupt
output
while
the
ST16C654DCQ64 provides continuous interrupt
output.
The 100 pin package provides additional
FIFO status outputs (TXRDY# and RXRDY# A-D),
separate infrared transmit data outputs (IRTX A-D)
and channel C external clock input (CHCCLK). The
ST16C654/654D is compatible with the industry
standard ST16C454 and ST16C654/554D.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
Pin-to-pin compatible with ST16C454, ST16C554
and TI’s TL16C554AFN and TL16C754BFN
Intel or Motorola Data Bus Interface select
Four independent UART channels
Register Set Compatible to 16C550
Data rates of up to 1.5 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
2.97V to 5.5V supply operation
Sleep Mode (200 uA typical)
Crystal oscillator or external clock input
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FIGURE 1. ST16C654 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
Data Bus
Interface
UART Channel A
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.97V to 5.5V VCC
GND
654 BLK
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
16/68#
CSB#
INTA
INTB
IOW#
IOR#
Reset
INTSEL
CHCCLK
TXRDY# A-D
RXRDY# A-D
UART Channel C
(same as Channel A)
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
UART Channel D
(same as Channel A)
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
CSC#
CSD#
INTC
INTD
CLKSEL
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