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参数资料
| 型号： | ST16C654CQ64TR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 19/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 标准包装： | 1,000 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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ST16C654/654D
xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
26
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high (if enabled by EFR bit-7).
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 11, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when the remote transmitter toggles the input pin (from low to high) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register (LSR bits 1-4 will clear but LSR bit-7 will not clear until
character(s) that generated the interrupt(s) has been emptied or cleared from FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR.
Special character interrupt is cleared by a read to ISR register or after next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C654D | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654DCQ64 | 制造商:Exar Corporation 功能描述: |
| ST16C654DCQ64-0A-EB | 功能描述:界面开发工具 Supports C654D 64 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| ST16C654DCQ64-F | 功能描述:UART 接口集成电路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C654DCQ64-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 64-LQFP |
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