参数资料
型号: ST16C554DCQ64-F
厂商: Exar Corporation
文件页数: 11/39页
文件大小: 0K
描述: IC UART FIFO 16B QUAD 64LQFP
标准包装: 160
特点: *
通道数: 4,QUART
FIFO's: 16 字节
规程: RS232
电源电压: 2.97 V ~ 5.5 V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
其它名称: 1016-1266
ST16C554/554D
19
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the
DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Reserved (Default 0)
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR BIT-7
FCR BIT-6
RECEIVE TRIGGER LEVEL
0
1
0
1
0
1
4
8
14
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