参数资料
| 型号： | ST16C580CQ48-F |
| 厂商： | Exar Corporation |
| 文件页数： | 13/39页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B 48TQFP |
| 标准包装： | 250 |
| 特点： | * |
| 通道数： | 1，UART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
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ST16C580
20
Rev. 1.22
Table 6, INTERRUPT SOURCE TABLE
Priority
[ ISR BITS ]
Level
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
000110
LSR (Receiver Line Status Register)
2
000100
RXRDY (Received Data Ready)
2
001100
RXRDY (Receive Data time out)
3
000010
TXRDY ( Transmitter Holding Register Empty)
4
000000
MSR (Modem Status Register)
5
010000
RXRDY (Received Xoff signal)/ Special character
6
100000
CTS, RTS change of state
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS,
RTS have been generated. Note that once set to a
logic 1, the ISR bit-4 will stay a logic 1 until Xon
character(s) are received.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFO’s
are enabled
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condition)
These two bits specify the word length to be transmitted
or received.
BIT-1
BIT-0
Word length
00
5
01
6
10
7
11
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
5,6,7,8
1
5
1-1/2
1
6,7,8
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
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| ST16C580IJ44 | 制造商:EXAR 制造商全称:EXAR 功能描述:UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
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