参数资料
| 型号： | ST16C654DIQ64-F |
| 厂商： | Exar Corporation |
| 文件页数： | 25/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 标准包装： | 160 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | 1016-1271 |
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xr
ST16C654/654D
REV. 5.0.2
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
31
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be set to a logic zero during 68 mode.
Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During loopback mode, it sets
OP2# internally to a logic 1.
Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During loopback mode, it sets OP2# internally
to a logic 0.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the 654 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR
bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an
error is in the RHR.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
TABLE 14: INT OUTPUT MODES
INTSEL
PIN
MCR
BIT-3
INT A-D OUTPUTS IN 16 MODE
0
Three-State
0
1
Active
1
X
Active
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相关代理商/技术参数 |
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| ST16C654IJ68 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C654IJ68-F | 功能描述:UART 接口集成电路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C654IJ68-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 68-PLCC |
| ST16C654IJ68TR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 68-Pin PLCC T/R 制造商:Exar Corporation 功能描述:2.97V to 5.5V Quad UART with 64 Byte FIFOs PLCC 68 制造商:Exar Corporation 功能描述:ST16C654IJ68TR-F |
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