参数资料
| 型号： | ST16C654DIQ64-F |
| 厂商： | Exar Corporation |
| 文件页数： | 50/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 标准包装： | 160 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | 1016-1271 |
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ST16C654/654D
xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
8
1.0 PRODUCT DESCRIPTION
The ST16C654 (654) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 1.5
Mbps. The ST16C654 can operate from 2.97 to 5.5 volts. The 654 is fabricated with an advanced CMOS
process.
Enhanced FIFO
The 654 QUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C554, or one byte in the ST16C454. The 654 is designed to work with high performance
data communication systems, that require fast data processing time. Increased performance is realized in the
654 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control mechanism.
This allows the external processor to handle more networking tasks within a given time. For example, the
ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character
length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the
receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the 654, the data buffer will not require
unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for
other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO
level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data
throughput performance especially when operating in a multi-channel system. The combination of the above
greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The 654 is capable of operation up to 1.5 Mbps at 5V with 16x internal sampling clock rate. The device can
operate at 5V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock
source of 24 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user
can set the prescaler bit for data rates of up to 921.6 kbps.
Enhanced Features
The rich feature set of the 654 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR
bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations
for the 64 pin 654 this feature is offered by two different LQFP packages. The ST16C654DCV operates in the
continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C654CV operates in
conjunction with MCR bit-3 by internally bonding INTSEL to GND.
The ST16C654 offers a clock prescaler select pin to allow system/board designers to preset the default baud
rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator.
It can then be overridden following initialization by MCR bit-7.
The 100 pin packages offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.
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相关代理商/技术参数 |
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| ST16C654IJ68 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C654IJ68-F | 功能描述:UART 接口集成电路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C654IJ68-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 68-PLCC |
| ST16C654IJ68TR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 68-Pin PLCC T/R 制造商:Exar Corporation 功能描述:2.97V to 5.5V Quad UART with 64 Byte FIFOs PLCC 68 制造商:Exar Corporation 功能描述:ST16C654IJ68TR-F |
| ST16C654IQ | 制造商:Exar Corporation 功能描述: |
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