参数资料
| 型号： | ST16C654IQ64-F |
| 厂商： | Exar Corporation |
| 文件页数： | 7/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 标准包装： | 160 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | 1016-1273 |
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xr
ST16C654/654D
REV. 5.0.2
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
15
2.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.10.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
相关PDF资料 |
PDF描述 |
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| XR16V654IV-F | IC UART FIFO 64B QUAD 64LQFP |
| ST16C654CQ64-F | IC UART FIFO 64B QUAD 64LQFP |
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| ST16C654IQ100-F | IC UART FIFO 64B QUAD 100QFP |
| XR16V654IL-F | IC UART FIFO 64B QUAD 48QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C654IQ64-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 64-LQFP 制造商:Exar Corporation 功能描述:IC, QUAD UART, 1.5MBPS, 5.5V, 64-LQFP |
| ST16C654IQ64TR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 64-Pin LQFP T/R 制造商:Exar Corporation 功能描述:ST16C654IQ64TR-F |
| ST16CF54 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Smartcard MCU With 4 KBytes EEPROM 512 Bits Modular Arithmetic Processor |
| ST16CQ32245TBR | 功能描述:开关 IC - 各种 Advanced Logic Signal Switch RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| ST16DD00 | 功能描述:拨动开关 TOGGLE RoHS:否 制造商:C&K Components 触点形式:DPDT 开关功能:ON - ON - ON 电流额定值: 电压额定值 AC:20 V 电压额定值 DC:20 V 功率额定值:0.4 VA 端接类型:V-Bracket 安装风格: 端子密封:Epoxy 触点电镀:Gold 照明:Not Illuminated |
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