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参数资料
| 型号： | ST6240BQ6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 49/73页 |
| 文件大小： | 1963K |
| 代理商： | ST6240BQ6/XXX |
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ST62T40B/E40B
POWER SUPPLY SUPERVISOR (Continued)
4.6.2 PSS Register
The PSS register permits control over the PSS de-
vice. The register can be addressed in the data
space as a RAM location at DAh. This register is
cleared after Reset.
PSS Status Control Register (PSSCR)
Address: DAh - Read/Write
Bit 7 = PIF. Interrupt flag bit. This bit is the interrupt
flag. This bit is set (resp. cleared) as soon as the
equality between nxVPSS and mxVDD/13 (resp.
(m+1)xVDD/13) occurs.
Bit 6 = PEI. Interrupt mask bit. This bit is the au-
thorization bit of the interrupt request: – If PEI is
set, the interrupt request can reach the Core. – If
PEI is cleared, the interrupt request cannot reach
the Core.
Bits 5-4 = PDV1, PDV0. Division rate selection bit.
The PDV1/0 bits are used to select the rate of divi-
sion
of
the
VDD
voltage
(mxVDD/13
or
(m+1)xVDD/13, according to the hysteresis).
Table 22. VDDVoltage division rate selection
bits
Bits 3-1 = PDR2, PDR1, PDR0. Division rate se-
lection bit. The PDR2/1/0 bits are used to inhibit
the PSS device and to select the division rate of
the PSS voltage (nxVPSS/13).
Bit 0 = D0. The PSS comparator output is valid 8
cycle times after the programming of the PDR2/1/0
bits. It is forced to zero in the meantime.
Table 23. PSS Voltage division rate selection bits
70
PIF
PEI
PDV1
PSS
PDV0
PSS
PDR2
PSS
PDR1
PSS
PDR0
PSS
D0
PDV1
PDV0
mxVDD/13
(m+ 1) xVDD/13
0
3xVDD/13
4xVDD/13
0
1
5xVDD/13
6xVDD/13
1
0
6xVDD/13
7xVDD/13
1
7xVDD/13
8xVDD/13
PDR2
PDR1
PDR0
PSS State
nxVPSS/13
0
IDLE
0
1
BUSY
4xVPSS/13
0
1
0
BUSY
5xVPSS/13
0
1
BUSY
6xVPSS/13
1
0
BUSY
7xVPSS/13
1
0
1
BUSY
VPSS
53
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