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参数资料
| 型号： | ST62E85BG1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQFP80 |
| 封装： | CERAMIC, QFP-80 |
| 文件页数： | 41/78页 |
| 文件大小： | 868K |
| 代理商： | ST62E85BG1 |
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Obsolete
Product(s)
- Obsolete
Product(s)
46/78
ST62T85B/E85B
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h
—
Read/Write
Bist 7-5 = PS2-PS0:
Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 16. Prescaler Division Ratio Selection
Bit 4 = D4:
Reserved. Must be kept reset.
Bit 3-2. Reserved. Must be cleared to zero
Bit 1-0 = CC1-CC0:
Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following Table
17:
Table 17. Clock Source Selection.
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: EBh
—
Read/Write
Bit 7-0 = D7-D0:
Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register. The ARRC re-
load/capture register is used to hold the auto-re-
load value which is automatically loaded into the
counter when overflow occurs.
AR Reload/Capture (ARRC)
Address: E9h
—
Read/Write
Bit 7-0 = D7-D0:
Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: EAh
—
Read/Write
Bit 7-0 = D7-D0:
Compare Data Bits. These are
the Compare register data bits.
70
PS2
PS1
PS0
D4
-
CC1
CC0
PS2
PS1
PS0
ARPSC Division Ratio
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
CC1
CC0
Clock Source
00
Fint
01
Fint Divided by 3
Others
Reserved
70
D7
D6
D5
D4
D3
D2
D1
D0
70
D7
D6
D5
D4
D3
D2
D1
D0
70
D7
D6
D5
D4
D3
D2
D1
D0
46
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