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参数资料
| 型号： | ST62P35BQ3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 4/82页 |
| 文件大小： | 617K |
| 代理商： | ST62P35BQ3/XXX |
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ST62T35B/E35B
MEMORY MAP (Cont’d)
1.3.6
Data
RAM/EEPROM
Bank
Register
(DRBR)
Address: CBh
—
Write only
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM
Page 1.
Bit2. This bit is not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0.
The selection of the bank is made by program-
ming the Data RAM Bank Switch register (DRBR
register) located at address CBh of the Data
Space according to Table 1. No more than one
bank should be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address CBh; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to se-
lect the desired 64-byte RAM/EEPROM bank of
the Data Space. The number of banks has to be
loaded in the DRBR register and the instruction
has to point to the selected location as if it was in
bank 0 (from 00h address to 3Fh address).
This register is not cleared during the MCU initial-
ization, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 5. Data RAM Bank Register Set-up
70
-
DRBR4 DRBR3
-
DRBR1 DRBR0
DRBR
ST62T35B
00
None
01
EEPROM Page 0
02
EEPROM Page 1
08
RAM Page 1
10h
RAM Page 2
other
Reserved
11
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