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参数资料
| 型号： | ST62P45BQ6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 22/72页 |
| 文件大小： | 514K |
| 代理商： | ST62P45BQ6/XXX |
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ST62T45B/E45B
IINTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
— Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB:
Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN:
Global Enable Interrupt. When this
bit is set to one, all interrupts are enabled. When
this bit is cleared to zero all the interrupts (exclud-
ing NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt Sources
Interrupt
sources
available
on
the
ST62E45B/T45B are summarized in theFigure 10
with associated mask bit to enable/disable the in-
terrupt request.
Table 10. Interrupt Requests and Mask Bits
70
-
LES
ESB
GEN
-
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
Interrupt
source
GENERAL
IOR
C8h
GEN
All Interrupts, excluding NMI
All
TIMER 1
TIMER 2
TSCR1
TSCR2
D4h
D7h
ETI
TMZ: TIMER Overflow
source 3
A/D CONVERTER
ADCR
D1h
EAI
EOC: End of Conversion
source 4
SPI
C2h
ALL
End of Transmission
source 1
Port PAn
ORPA-DRPA
C0h-C4h
ORPAn-DRPAn
PAn pin
source 2
Port PBn
ORPB-DRPB
C1h-C5h
ORPBn-DRPBn
PBn pin
source 2
Port PCn
ORPC-DRPC
C6h-CFh
ORPCn-DRPCn
PCn pin
source 2
32kHz OSC
32OCR
DBh
EOSCI
OSCEOC
source 3
28
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