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参数资料
| 型号： | ST62P45BQ6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 38/72页 |
| 文件大小： | 514K |
| 代理商： | ST62P45BQ6/XXX |
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ST62T45B/E45B
TIMER 1& 2 (Cont’d)
4.2.6 TIMER 2 Registers
Timer Status Control Register (TSCR)
Address: 0D7h
— Read/Write
Bit 7 = TMZ:
Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This
bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI:
Enable Timer Interrup
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
Bit 5 = D5:
Reserved
Must be set to “1”.
Bit 4 = D4
Do not care.
Bit 3 = PSI:
Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its
counting. When PSI=“0” the prescaler is set to
7Fh and the counter is inhibited. When PSI=“1”
the prescaler is enabled to count downwards. As
long as PSI=“0” both counter and prescaler are
not running.
Bit 2, 1, 0 = PS2, PS1, PS0:
Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
Table 16. Prescaler Division Factors
Timer Counter Register (TCR)
Address: 0D6h
—
Read/Write
Bit 7-0 = D7-D0:
Counter Bits.
Prescaler Register PSC
Address: 0D5h
—
Read/Write
Bit 7 = D7: Always read as ”0”.
Bit 6-0 = D6-D0: Prescaler Bits.
70
TMZ
ETI
D5
D4
PSI
PS2
PS1
PS0
PS2
PS1
PS0
Divided by
00
0
1
00
1
2
01
0
4
01
1
8
10
0
16
10
1
32
11
0
64
11
1
128
70
D7
D6
D5
D4
D3
D2
D1
D0
70
D7
D6
D5
D4
D3
D2
D1
D0
42
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