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参数资料
| 型号： | ST62P65CM3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | 0.300 INCH, PLASTIC, SOP-28 |
| 文件页数： | 27/86页 |
| 文件大小： | 970K |
| 代理商： | ST62P65CM3/XXX |
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ST62T55C ST62T65C/E65C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused.
Bit 6 = LES:
Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB:
Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN:
Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the Table 9 with associated mask
bit to enable/disable the interrupt request.
Table 9Interrupt Requests and Mask Bits
70
-
LES
ESB
GEN
-
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
Interrupt
vector
GENERAL
IOR
C8h
GEN
All Interrupts, excluding NMI
TIMER
TSCR1
D4h
ETI
TMZ: TIMER Overflow
Vector 4
A/D CONVERTER
ADCR
D1h
EAI
EOC: End of Conversion
Vector 4
AR TIMER
ARMC
D5h
OVIE
CPIE
EIE
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
Vector 3
SPI
SPIMOD
E2h
SPIE
SPRUN: End of Transmission
Vector 2
Port PAn
ORPA-DRPA
C0h-C4h
ORPAn-DRPAn
PAn pin
Vector 1
Port PBn
ORPB-DRPB
C1h-C5h
ORPBn-DRPBn
PBn pin
Vector 1
Port PCn
ORPC-DRPC
C2h-C6h
ORPCn-DRPCn
PCn pin
Vector 2
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