参数资料
型号: ST6375B1/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封装: SHRINK, PLASTIC, DIP-42
文件页数: 18/84页
文件大小: 861K
代理商: ST6375B1/XXX
25/84
ST6365, ST6375, ST6385 ST6367, ST6377, ST6387
INTERRUPTS (Cont’d)
The interrupt routine begins usually by the identifi-
cation of the device that has generated the inter-
rupt request. The user should save the registers
which are used inside the interrupt routine (that
holds relevant data) into a software stack. After the
RETI instruction execution, the Core carries out
the previous actions and the main routine can con-
tinue.
3.4.5 ST638x Interrupt Details
IR Interrupt (#0). The IRIN/PC6 Interrupt is con-
nected to the first interrupt #0 (NMI, 0FFCh). If the
IRINT interrupt is disabled at the Latch circuitry,
then it will be high. The #0 interrupt input detects a
high to low level. Note that once #0 has been
latched, then the only way to remove the latched
#0 signal is to service the interrupt. #0 can inter-
rupt the other interrupts. A simple latch is provided
from the PC6(IRIN) pin in order to generate the IR-
INT signal. This latch can be triggered by either
the positive or negative edge of IRINT signal. IR-
INT is inverted with respect to the latch. The latch
can be read by software and reset by software.
TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is
connected to the interrupt #1 (0FF6h). The TIMER
2 interrupt generates a low level (which is latched
in the timer). Only the low level selection for #1 can
be used. Bit 6 of the interrupt option register C8h
has to be set.
VSYNC Interrupt (#2). The VSYNC Interrupt is
connected to the interrupt #2. When disabled the
VSYNC INT signal is low. The VSYNC INT signal
is inverted with respect to the signal applied to the
VSYNC pin. Bit 5 of the interrupt option register
C8h is used to select the negative edge (ES2=0)
or the positive edge (ES2=1); the edge will depend
on the application. Note that once an edge has
been latched, then the only way to remove the
latched signal is to service the interrupt. Care must
be taken not to generate spurious interrupts. This
interrupt may be used to synchronize the VSYNC
signal in order to change characters in the OSD
only when the screen is on vertical blanking (if de-
sired). This method may also be used to blink
characters.
TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is
connected to the fourth interrupt #3 (0FF2h) which
detects a low level (latched in the timer).
PWR Interrupt (#4). The PWR Interrupt is con-
nected to the fifth interrupt #4 (0FF0h). If the
PWRINT is disabled at the PWR circuitry, then it
will be high. The #4 interrupt input detects a low
level. A simple latch is provided from the PC4
(PWRIN)pin in order to generate the PWRINT sig-
nal. This latch can be triggered by either the posi-
tive or negative edge of the PWRIN signal.
PWRINT is inverted with respect to the latch. The
latch can be reset by software.
Notes: Global disable does not reset edge sensi-
tive interrupt flags. These edge sensitive interrupts
become pending again when global disabling is re-
leased. Moreover, edge sensitive interrupts are
stored in the related flags also when interrupts are
globally disabled, unless each edge sensitive in-
terrupt is also individually disabled before the in-
terrupting event happens. Global disable is done
by clearing the GEN bit of Interrupt option register,
while any individual disable is done in the control
register of the peripheral. The on-chip Timer pe-
ripherals have an interrupt request flag bit (TMZ),
this bit is set to one when the device wants to gen-
erate an interrupt request and a mask bit (ETI) that
must be set to one to allow the transfer of the flag
bit to the Core.
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