参数资料
型号: ST6382B1/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PDIP42
封装: PLASTIC, SDIP-42
文件页数: 67/82页
文件大小: 1651K
代理商: ST6382B1/XXX
Obsolete
Product(s)
- Obsolete
Product(s)
7/82
ST6388, ST63E88, ST63T88
DA0-DA5. These pins are the six PWM D/A out-
puts of the 6-bit on-chip D/A converters. These
lines have open-drain outputs with 12V drive. The
output repetition rate is 31.25KHz (with 8MHz
clock).
OSDOSCin, OSDOSCout. These are the On
Screen Display oscillator terminals. An oscillation
capacitor and coil network have to be connected to
provide the right signal to the OSD.
HSYNC, VSYNC. These are the horizontal and
vertical synchronization pins. The active polarity of
these pins to the OSD macrocell can be selected
by the user as ROM mask option. If the device is
specified to have negative logic inputs, then these
signals are low the OSD oscillator stops. If the de-
vice is specified to have positive logic inputs, then
when these signals are high the OSD oscillator
stops. VSYNC is also connected to the VSYNC in-
terrupt.
R, G, B, BLANK. Outputs from the OSD. R, G and
B are the color outputs while BLANK is the blank-
ing output. All outputs are push-pull.
VS. This is the output pin of the on-chip 14-bit volt-
age synthesis tuning cell (VS). The tuning signal
present at this pin gives an approximate resolution
of 40KHz per step over the UHF band. This line is
a push-pull output with standard drive.
Figure 2. ST6388 Pin Configuration
Table 2. Pin Summary
VR01375
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DA0
DA1
DA2
DA3
DA4
DA5
AD1/PB1
AD2/PB2
AD3/PB3
AD4/PB4
AD5/PB5
AD6/PB6
PA0
PA1
PA2
PA3
PA4
PA5
PA6 (HD0)
PA7 (HD1)
VSS
VDD
PC0/SCL
PC1/SDA
PC2
PC3/SEN
PC4/PWRIN
PC5
VS
OSCin
OSCout
TEST/VPP
(1)
VSYNC
BLANK
B
G
R
PC6/IRIN
(1) This pin is also the VPP input for OTP/EPROM devices
RESET
HSYNC
OSDOSCout
OSDOSCin
Pin Function
Description
DA0 to DA5
Output, Open- Drain, 12V
VS
Output, Push- Pull
R, G, B, BLANK
Output, Push- Pull
HSYNC, VSYNC
Input, Pull- up, Schmitt Trigger
OSDOSCin
Input, High Impedance
OSDOSCout
Output, Push- Pull
TEST
Input, Pull- Down
OSCin
Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
OSCout
Output, Push- Pull
RESET
Input, Pull- up, Schmitt Trigger Input
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