参数资料
型号: ST6392B1
厂商: 意法半导体
英文描述: 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
中文描述: 8位微控制器HCMOS电视频率合成带OSD
文件页数: 34/68页
文件大小: 560K
代理商: ST6392B1
PS2
PS1
PS0
Divided By
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Table 9. Prescaler DivisionFactors
TSCR
Imer 1&2 Status ControlRegisters
DAh Timer 1,DCh Timer 2,
Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
PS0 =PrescalerMux. Select
PS1 =PrescalerMux. Select
PS2 =PrescalerMux. Select
PSI =PrescalerInitialize Bit
D4 = TimersEnable Bit
*
D5 = TimersEnable Bit
*
ETI = Enable TimerInterrupt
TMZ = TimerZero Bit
*
Only Available in TSCR1
Figure34. Timer Status Control Registers
TIMERS
(Continued)
TMZ.
Low-to-high transitionindicatesthatthetimer
count register has decrementtozero. This bitmust
be cleared by user software before to start with a
new count.
ETI.
This bit, when set, enablesthe timer interrupt
(vector#3forTimer1,vector#1forTimer2)request.
If ETI=0the timer interruptis disabled.IfETI=1 and
TMZ= 1an interruptrequestis generated.
D5.
This is the timers enable bit D5. It must be
cleared to0 togetherwith aset to 1 of bit D4 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D4.
This is the timers enable bit D4. This bit must
be setto 1 togetherwith aclear to 0 of bitD5 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D5
D4
Timers
0
0
Disabled
0
1
Enabled
1
X
Reserved
PS1.
Used to initialize the prescaler and inhibit its
countingwhilePSI=0theprescalerissetto7Fhand
the counteris inhibited. WhenPSI = 1the prescaler
is enabledto count downwards.As long as PSI= 0
bothcounterandprescalerarenot running.
PS2-PS0.
Thesebits select thedivision ratioof the
prescaler register.(see Table 9)
The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
written in TSCR1 by user’s software to enable the
operation of Timer 1 andTimer 2.
TCR
Timer Counter1&2 Register
D3h Timer 1, DBh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D7 -D0 =Counter bits
Figure 35. Timer CounterRegisters
PSC
TimerPrescaler 1&2 Register
D2h Timer 1, DAh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D6 -D0 =Prescalerbits
Always read as “0”
Figure 36. Timer CounterRegisters
ST6391,92,93,95,97,99
30/64
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ST6393B1 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
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ST6391B1 MOSFET; Transistor Polarity:Dual N Channel; Continuous Drain Current, Id:2.6A; On-Resistance, Rds(on):0.18ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No
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