参数资料
型号: ST72121J2T3/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封装: PLASTIC, TQFP-44
文件页数: 15/87页
文件大小: 1365K
代理商: ST72121J2T3/XXX
22/87
ST72121
3.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
Register Address: 0020h
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = PEI[3:2]
External Interrupt EI3 and EI2
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to Table 6.
Table 6. EI2 and EI3 External Interrupt Polarity
Options
Bit 5 = MCO
Main Clock Out
This bit is set and cleared by software. When set it
allows to output the Internal Clock on PF0 I/O.
0 - PF0 is a normal I/O port.
1- fCPU outputs on PF0 pin.
Bit 4:3 = PEI1-PEI0
External Interrupt EI1 and EI0
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to Table 7.
Table 7. EI0 and EI1 External Interrupt Polarity
Options
Bit 2:1 = PSM[1:0]
Prescaler for Slow Mode
These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.
Table 8. fCPU Value in Slow Mode
Bit 0 = SMS
Slow Mode Select
This bit is set and cleared by software.
0: Normal Mode - fCPU =fOSC/2
(Reset state)
1: Slow Mode - the fCPU value is determined by the
PSM1 and PSM0 bits.
70
PEI3 PEI2 MCO PEI1 PEI0 PSM1
PSM0 SMS
MODE
PEI3
PEI2
Falling edge and low level
(Reset state)
00
Falling edge only
1
0
Rising edge only
0
1
Rising and falling edge
1
MODE
PEI1
PEI0
Falling edge and low level
(Reset state)
00
Falling edge only
1
0
Rising edge only
0
1
Rising and falling edge
1
fCPU Value
PSM1
PSM0
fOSC /4
0
fOSC /16
0
1
fOSC /8
1
0
fOSC /32
1
22
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