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| 型号： | ST72311N2T3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | PLASTIC, TQFP-64 |
| 文件页数： | 37/92页 |
| 文件大小： | 624K |
| 代理商： | ST72311N2T3/XXX |
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ST72311
16-BIT TIMER (Cont’d)
4.3.3.7 Pulse Width Modulation Mode
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corre-
sponding to the period of the signal.
2. Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC1-CC0) (see Table
15).
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
– t = Desired output compare period (seconds)
–fCPU = Internal clock frequency (see Miscella-
neous register)
–
tPRESC = Timer clock prescaler (CC1-CC0
bits , see Table 15)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 32).
Note: After a write instruction to the OC
iHR regis-
ter, the output compare function is inhibited until
the OC
iLR register is also written.
The ICF1 bit is set by hardware when the counter
reaches the OC2R value and can produce a timer
interrupt if the ICIE bit is set and the I bit is cleared.
Therefore the Input Capture 1 function is inhibited
but the Input Capture 2 is available.
The OCF1 and OCF2 bits cannot be set by hard-
ware in PWM mode therefore the Output Compare
interrupt is inhibited.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 32. Pulse Width Modulation Mode Timing
OC
iR Value =
t * fCPU
tPRESC
-5
Counter
OCMP1 = OLVL2
Counter
= OC2R
OCMP1 = OLVL1
When
= OC1R
Pulse Width Modulation cycle
Counter is reset
to FFFCh
ICF1 bit is set
COUNTER
34E2
FFF C FFF D FFFE
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OCMP1
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
42
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