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参数资料
| 型号： | ST72311N4T6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | PLASTIC, TQFP-64 |
| 文件页数： | 69/92页 |
| 文件大小： | 624K |
| 代理商： | ST72311N4T6/XXX |
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ST72311
8-BIT A/D CONVERTER (ADC) (Cont’d)
4.6.3 Functional Description
The high level reference voltage VDDA must be
connected externally to the VDD pin. The low level
reference voltage VSSA must be connected exter-
nally to the VSS pin. In some devices (refer to de-
vice pin out description) high and low level refer-
ence voltages are internally connected to the VDD
and VSS pins.
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Characteristics:
The conversion is monotonic meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to VDD
(voltage reference high) then results = FFh (full
scale) without overflow indication.
If input voltage
≤ V
SS (voltage reference low) then
the results = 00h.
The conversion time is 64 CPU clock cycles in-
cluding a sampling time of 31.5 CPU clock cycles.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
Where Reference Voltage is VDD -VSS.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
Procedure:
Refer to the CSR and DR register description sec-
tion for the bit definitions.
Each analog input pin must be configured as input,
no pull-up, no interrupt. Refer to the I/O ports
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the CSR register:
– Select the CH2 to CH0 bits to assign the ana-
log channel to convert. Refer to Table 20.
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
s). It then performs a continuous conversion
of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register.
A write to the CSR register aborts the current con-
version, resets the COCO bit and starts a new
conversion.
Notes: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
The A/D converter is not affected by WAIT mode.
When the MCU enters HALT mode with the A/D
converter enabled, the converter is disabled until
the HALT mode is exited and the start-up delay
has elapsed. A stabilisation time is also required
before accurate conversions can be performed.
Digital result =
255 x Input Voltage
Reference Voltage
71
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