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ST72311
3.2 RESET
3.2.1 Introduction
There are four sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
– Low Voltage Detection Reset (internal source)
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
3.2.2 External Reset
The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low to reset the whole application.
3.2.3 Reset Operation
The duration of the Reset condition, which is also
reflected on the output pin, is fixed at 4096 internal
CPU Clock cycles. A Reset signal originating from
an external source must have a duration of at least
1.5 internal CPU Clock cycles in order to be recog-
nised. At the end of the Power-On Reset cycle, the
MCU may be held in the Reset condition by an Ex-
ternal Reset signal. The RESET pin may thus be
used to ensure VDD has risen to a point where the
MCU can operate correctly before the user pro-
gram is run. Following a Power-On Reset event, or
after exiting Halt mode, a 4096 CPU Clock cycle
delay period is initiated in order to allow the oscil-
lator to stabilise and to ensure that recovery has
taken place from the Reset state.
During the Reset cycle, the device Reset pin acts
as an output that is pulsed low. In its high state, an
internal pull-up resistor is connected to the Reset
pin. This resistor can be pulled low by external cir-
cuitry to reset the device.
The Reset pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, the best external network is a double
capacitive decoupling consisting of 0.1
Fto V
SS
and 0.1
Fto V
DD.
Figure 12. Reset Block Diagram
INTERNAL
RESET
WATCHDOG RESET
OSCILLATOR
SIGNAL
COUNTER
RESET
TO ST7
RESET
POWER-ON RESET
VDD
LOW VOLTAGE DETECTOR RESET
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