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参数资料
| 型号： | ST72311R9T3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, TQFP-64 |
| 文件页数： | 62/152页 |
| 文件大小： | 1909K |
| 代理商： | ST72311R9T3/XXX |
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ST72311R, ST72511R, ST72532R
17/152
DATA EEPROM (Cont’d)
3.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 5 describes these different memory
access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
Note: In order to ensure the correct read out of the
EEPROM over the entire temperature range, the
cell whose contents will be read, must be read
twice in compliance with the following conditions:
s
a first reading must be immediately followed by
a second reading
– all interrupts must be disabled until the two
readings are performed
– no other instructions are allowed between the
two reading instructions
s
the data of the first reading has to be discarded
The described procedure corresponds to the fol-
lowing code sequence:
sim
ld A,eeprom_var
rim
where eeprom_var adresses the EERPOM cell to
be read. Any of the ST7 addressing modes may be
used.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit. It is not possible to read the latched data.
This note is ilustrated by the Figure 6.
Figure 5. Data EEPROM Programming Flowchart
READ MODE
LAT=0
PGM=0
WRITE MODE
LAT=1
PGM=0
READ BYTES
IN EEPROM AREA
WRITEUPTO 16 BYTES
IN EEPROM AREA
(with the same 12 MSB of the address)
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
LAT
INTERRUPT GENERATION
IF IE=1
0
1
CLEARED BY HARDWARE
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| ST72311R7T6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72311R9T6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES |
| ST72311R9T6/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST72311R9T6S | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES |
| ST72311R9T6S/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST72311R9T7 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES |
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