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| 型号： | ST72324BLK4BA/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件页数： | 55/151页 |
| 文件大小： | 1209K |
| 代理商： | ST72324BLK4BA/XXX |
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ST72F324L, ST72324BL
148/151
15 KNOWN LIMITATIONS
15.1 ALL FLASH AND ROM DEVICES
15.1.1 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to Section 6.2 on page
23.
15.1.2 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.1.3
Clearing
active
interrupts
outside
interrupt routine
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
Note: clearing the related interrupt mask will not
generate an unwanted reset
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
– The interrupt flag is cleared within any interrupt
routine
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request.
Example:
SIM
reset interrupt flag
RIM
Nested interrupt context:
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
– The interrupt flag is cleared within any interrupt
routine with higher or identical priority level
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
PUSH CC
SIM
reset interrupt flag
POP CC
15.1.4 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
15.1.5 ADC Conversion Spurious Results
Spurious conversions occur with a rate lower than
50 per million. Such conversions happen when the
measured voltage is just between 2 consecutive
digital values.
Workaround
A software filter should be implemented to remove
erratic conversion results whenever they may
cause unwanted consequences.
In order to have the accuracy specified in the da-
tasheet, the first conversion after a ADC switch-on
has to be ignored.
1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72324BLK4T1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324BLK4T5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324BLK4T6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
| ST72324BLK4TA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE |
| ST72324BLS2B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface |
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