- 您现在的位置：买卖IC网 > PDF目录69373 > ST72671N4B1/XXX (STMICROELECTRONICS) 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP56 PDF资料下载
参数资料
| 型号： | ST72671N4B1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | 0.600 INCH, SHRINK, PLASTIC, DIP-56 |
| 文件页数： | 11/101页 |
| 文件大小： | 608K |
| 代理商： | ST72671N4B1/XXX |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页
17/101
ST72671
3.3 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in Table 6 and a non-maskable software in-
terrupt (TRAP). The Interrupt processing flowchart
is shown in Figure 11.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
Table 6 for vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt can not be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
In the case several interrupts are simultaneously
pending, an hardware priority defines which one
will be serviced first (see Table 6).
Non Maskable Software Interrupts
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 11.
Interrupts and Low power mode
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
Halt low power mode (refer to the “Exit from HALT“
column in Table 6).
External Interrupts
External interrupt vectors can be loaded in the PC
register if the corresponding external interrupt oc-
curred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity can be selected
through the Miscellaneous register or Interrupt
register (if available) (seeSection 3.4.5).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared on entering the interrupt service routine.
More than one input pin can be connected to the
same interrupt request (depending on the device).
In this case, all inputs configured as interrupt are
logically ORed.
Warning: The type of polarity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the EI source. In case of an ORed source,
a low level on an I/O pin configured as input with
interrupt, masks the interrupt request even in case
of rising-edge polarity.
Peripheral Interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– writing “0” to the corresponding bit in the status
register or
– an access to the status register while the flag is
set followed by a read or write of an associated
register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
相关PDF资料 |
PDF描述 |
|---|---|
| ST7FL19F1MATRE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
| ST7FL34F2MCE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
| ST7FL38F2MAE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
| ST7FL35F2UCRE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20 |
| ST7FL38F2MAXE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST7267C8T1L | 制造商:STMicroelectronics 功能描述: |
| ST72681/R12 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE BUS-POWERED USB 2.0 FLASH DR - Trays |
| ST72681/S13 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE - Trays |
| ST7271 | 制造商:Panasonic Industrial Company 功能描述:IC |
| ST7271N5B1-CLF | 制造商:STMicroelectronics 功能描述: |
发布紧急采购，3分钟左右您将得到回复。