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参数资料
型号： ST72C254G1B7
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 6 MHz, MICROCONTROLLER, PDIP32
封装： SHRINK, PLASTIC, DIP-32
文件页数： 57/136页
文件大小： 929K
代理商： ST72C254G1B7
ST72104G, ST72215G, ST72216G, ST72254G
27/136
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 20).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 24) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 19).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 16.1 ”OPTION BYTES” on page 130 for
more details).
Figure 19. HALT Mode Timing Overview
Figure 20. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt Mapping,” on page 24 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
HALT
RUN
4096 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
HALT INSTRUCTION
RESET
INTERRUPT 3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
1
ON
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
X 4)
ON
4096 CPU CLOCK CYCLE
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1)
0
WATCHDOG
RESET
1
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相关代理商/技术参数
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