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参数资料
型号： ST72F321J9T7
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封装： 10 X 10 MM, PLASTIC, TQFP-44
文件页数： 15/176页
文件大小： 1112K
代理商： ST72F321J9T7
ST72321J
111/176
10.7 I2C BUS INTERFACE (I2C)
10.7.1 Introduction
The I2C Bus Interface serves as an interface be-
tween the microcontroller and the serial I2C bus. It
provides both multimaster and slave functions,
and controls all I2C bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast I2C
mode (400kHz).
10.7.2 Main Features
s
Parallel-bus/I2C protocol converter
s
Multi-master capability
s
7-bit/10-bit Addressing
s
Transmitter/Receiver flag
s
End-of-byte transmission flag
s
Transfer problem detection
I
2C Master Features:
s
Clock generation
s
I2C bus busy flag
s
Arbitration Lost Flag
s
End of byte transmission flag
s
Transmitter/Receiver Flag
s
Start bit detection flag
s
Start and Stop generation
I
2C Slave Features:
s
Stop bit detection
s
I2C bus busy flag
s
Detection of misplaced start or stop condition
s
Programmable I
2C Address detection
s
Transfer problem detection
s
End-of-byte transmission flag
s
Transmitter/Receiver flag
10.7.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
2C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I2C bus
and a Fast I2C bus. This selection is made by soft-
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 61.
Figure 60. I
2C BUS Protocol
SCL
SDA
12
8
9
MSB
ACK
STOP
START
CONDITION
VR02119B
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相关代理商/技术参数
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ST72F321J9TCE 制造商:STMicroelectronics 功能描述:
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