参数资料
型号: ST72F321J9T7
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封装: 10 X 10 MM, PLASTIC, TQFP-44
文件页数: 78/176页
文件大小: 1112K
代理商: ST72F321J9T7
ST72321J
169/176
ST72321J DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPT8 = PLL OFF
PLL activation
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequen-
cy between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT11:9) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
OPT7= WDG HALT
Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CSS
Clock security system on/off
This option bit enables or disables the clock secu-
rity system function (CSS) which include the clock
filter and the backup safe oscillator.
0: CSS enabled
1: CSS disabled
When enabled, the selected “OSC RANGE” is
used to determine which is the selected operating
frequency range to switch to the backup oscillator
when the frequency is out of range.
OPT4:3= VD[1:0]
Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD.
OPT0= FMP_R
Flash memory read-out protection
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
induce the whole user memory erasing first.
0: read-out protection enabled
1: read-out protection disabled
Typ. Freq.
Range
OSCRANGE Compared frequencies to
decide to switch to the
backup oscillator
10
1~2MHz
0
2 x fCPU
fSFOSC
2~4MHz
0
1
fCPU
4~8MHz
1
0
fCPU/2
8~16MHz
1
fCPU/4
Selected Low Voltage Detector
VD1
VD0
LVD and AVD Off
1
Lowest Voltage Threshold (VDD~3.5V)
1
0
Medium Voltage Threshold (VDD~4V)
0
1
Highest Voltage Threshold (VDD~5V)
0
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