参数资料
型号: ST72F324LJ2T5
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封装: 10 X 10 MM, TQFP-44
文件页数: 96/154页
文件大小: 3519K
代理商: ST72F324LJ2T5
ST72324Lxx
46/154
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
10.1.2 Main Features
Programmable free-running downcounter
Programmable reset
Reset (if watchdog activated) when the T6 bit
reaches zero
Optional
reset
on
HALT
instruction
(configurable by option byte)
Hardware Watchdog selectable by option byte
10.1.3 Functional Description
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 fOSC2 cycles (approx.), and the
length of the timeout period can be programmed
by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling the reset pin low for typically
30s.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This down-
counter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 29. Ap-
proximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 30).
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 28. Watchdog Block Diagram
RESET
WDGA
6-BIT DOWNCOUNTER (CNT)
fOSC2
T6
T0
WDG PRESCALER
WATCHDOG CONTROL REGISTER (WDGCR)
DIV 4
T1
T2
T3
T4
T5
12-BIT MCC
RTC COUNTER
MSB
LSB
DIV 64
0
5
6
11
MCC/RTC
TB[1:0] bits
(MCCSR
Register)
1
相关PDF资料
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ST72324BLJ4B5/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
ST72324BLJ4B6/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
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