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参数资料
型号： ST72P621J4T1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO34
封装： PLASTIC, SO-34
文件页数： 105/136页
文件大小： 2475K
代理商： ST72P621J4T1
ST7262
70/136
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.3 Receiver
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 46).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
Clearing the RDRF bit is performed by the following
software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SPI han-
dles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Overrun Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
RDR register as long as the RDRF bit is not
cleared.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In
the case of start bit detection, the NF flag is set on
the basis of an algorithm combining both valid
edge detection and three samples (8th, 9th, 10th).
Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
tection as well as three valid samples.
When noise is detected in a frame:
– The NF flag is set at the rising edge of the RDRF
bit.
– Data is transferred from the Shift register to the
SCIDR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The NF flag is reset by a SCISR register read op-
eration followed by a SCIDR register read opera-
tion.
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this
case, the NF flag may be ignored by the applica-
tion software when the first valid byte is received.
See also Section 10.5.4.10.
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