参数资料
型号: ST72P63BE6M1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-24
文件页数: 131/145页
文件大小: 2984K
代理商: ST72P63BE6M1
ST7263BDx ST7263BHx ST7263BKx ST7263BE
86/145
12.5 IC bus interface (IC)
12.5.1 Introduction
The IC Bus Interface serves as an interface be-
tween the microcontroller and the serial IC bus. It
provides both multimaster and slave functions,
and controls all IC bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast IC
mode (400 kHz).
12.5.2 Main features
Parallel-bus/IC protocol converter
Multi-master capability
7-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
IC master features:
Clock generation
IC bus busy flag
Arbitration Lost flag
End of byte transmission flag
Transmitter/Receiver flag
Start bit detection flag
Start and Stop generation
IC slave features:
Stop bit detection
IC bus busy flag
Detection of misplaced start or stop condition
Programmable IC Address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
12.5.3 General description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the IC
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard IC bus
and a Fast IC bus. This selection is made by soft-
ware.
Mode selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7-bit), and the General Call
address. The General Call address detection may
be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
Figure 43. IC bus protocol
SCL
SDA
12
8
9
MSB
ACK
STOP
START
CONDITION
VR02119B
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