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参数资料
型号： ST72P63BE6M1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封装： 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-24
文件页数： 2/145页
文件大小： 2984K
代理商： ST72P63BE6M1
ST7263BDx ST7263BHx ST7263BKx ST7263BE
10/145
Figure 6. 24-pin SO package pinout
RESET (see Note 1): bidirectional. This active low
signal forces the initialization of the MCU. This
event is the top priority non maskable interrupt.
This pin is switched low when the Watchdog is trig-
gered or the VDD is low. It can be used to reset ex-
ternal peripherals.
OSCIN/OSCOUT:
input/output
oscillator
pin.
These pins connect a parallel-resonant crystal, or
an external source, to the on-chip oscillator.
VDD/VSS (see Note 2): main power supply and
Ground voltages.
VDDA/VSSA (see Note 2): power supply and
ground voltages for analog peripherals.
Alternate Functions: Several pins of the I/O ports
assume software programmable alternate func-
tions as shown in the pin description.
Note 1: Adding two 100 nF decoupling capacitors
on the Reset pin (respectively connected to V
DD
and V
SS) will significantly improve product electro-
magnetic susceptibility performance.
Note 2: To enhance the reliability of operation, it is
recommended that VDDA and VDD be connected to-
gether on the application board. This also applies
to VSSA and VSS.
Note 3: The USBOE alternate function is mapped
on port C2 in 32/34/48 pin devices. In SO24 devic-
es it is mapped on Port B1.
Note 4: The timer OCMP1 alternate function is
mapped on Port A6 in 32/34/48 pin devices. In
SO24 devices it is not available.
Legend / Abbreviations for Table 2 and Table 3:
Type:
I = input, O = output, S = supply
In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger
Output level:
10mA = 10mA high sink (Fn N-buffer only)
25mA = 25mA very high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output:
OD = open drain, PP = push-pull, T = True open drain
The RESET configuration of each pin is shown in
bold. This configuration is kept as long as the de-
vice is under reset state.
14
13
11
12
15
16
17
18
PA2(25mA)/SCL/ICCCLK
PA1(25mA)/SDA/ICCDATA
PA0/MCO
VSSA
PA7/OCMP2/IT4
PA5/ICAP2/IT2
PA4/ICAP1/IT1
1
2
3
4
5
6
7
8
9
10
VDD
RDI/PC0
TDO/PC1
VSS
PA3/EXTCLK
IT7/PB6(10mA)
19
20
VPP/TEST
PB3(10mA)
PB2(10mA)
USBDP
RESET/
OSCOUT
USBOE/PB1(10mA)
PB0(10mA)
OSCIN
21
22
23
24
USBDM
USBVcc
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