参数资料
型号: ST72PSCR1x4T1
厂商: 意法半导体
英文描述: 8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER
中文描述: 8位低功耗,全速USB微控制器与16K的闪存,768内存,智能卡的I /楼,计时器
文件页数: 92/102页
文件大小: 1413K
代理商: ST72PSCR1X4T1
ST7SCR
92/102
16 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in ROM
versions and in user programmable versions (High
Density FLASH).
FLASH devices are shipped to customers with a
default content (FFh).
This implies that FLASH devices have to be con-
figured by the customer using the Option Byte
while the ROM devices are factory-configured.
16.0.1 Option Bytes
The 8 option bits from the flash are programmed
through the static option byte SOB1. The descrip-
tion of each of these 8 bits is given below.
Static option Byte (SOB1)
OPT7:6 = Reserved
OPT5=
WDGSW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always activated)
1: Software (watchdog to be activated by software)
OPT4 =
NEST
Interrupt Controller
This bit enables the nested Interrupt Controller.
0: Nested interrupt controller disabled
1: Nested interrupt controller enabled
OPT3 =
ISOCLK
Clock source selection
0: Card clock is generated by the divider (48MHz/
12 = 4MHz).
1: Card clock is generated by the oscillator.
OPT2 =
RETRY
Number of Retries for UART ISO
0: In case of an erroneous transfer, character is
transmitted 4 times.
1: In case of an erroneous transfer, character is
transmitted 5 times.
OPT1 = Reserved, must be kept at 1.
OPT0 =
FMP_R
Flash memory read-out protec-
tion
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
induce the whole user memory erasing first.
0 : read-out protection enabled
1 : read-out protection disabled
OPT
7
6
5
4
3
2
1
OPT
0
--
--
WDG-
SW
NEST ISOCLK RETRY
-
FMP_R
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