22/101
ST72671
3.4.5 Register Description
MISCELLANEOUS REGISTER (MISCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = EI4F
Falling Edge Detector Flag.
This bit is set by hardware when a falling edge oc-
curs on the pin assigned to EI4. An interrupt is
generated if EI4ITE=1 It is cleared by software.
0: No falling edge detected on EI4
1: Falling edge detected on EI4
Bit 6 = EI4ITE EI4 Interrupt Enable.
This bit is set and cleared by software.
0: EI4 interrupt disabled
1: EI4 interrupt enabled
Bit 5 = SMS
Slow Mode Select.
This bit is set and cleared by software. It is used to
select the slow or fast mode CPU frequency.
0: fCPU = Oscillator frequency / 6 (slow mode)
1: fCPU = Oscillator frequency / 3 (normal mode)
Bit 4: 1 = Reserved
Bit 0 = POC0 PWM/BRM Output Configuration Bit.
This bits is set and cleared by software. They se-
lect the PWM/BRM output configuration for pins
DA1-DA4.
0: Push-pull
1: Open drain
Note.
DA0 is only Push-Pull Output.
INTERRUPT REGISTER (ITRFRE)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:5 = EI0F, EI1F, EI2F
Falling Edge Detector
Flags.
These bits are set by hardware when a falling
edge occurs on the pins assigned to EI0, EI1 or
EI2. They are cleared by software. When any of
these bits are set, an interrupt is generated if the
corresponding ITE bit =1 and the I bit in the CC
register = 0.
0: No falling edge detected
1: Falling edge detected
Bit 4 = EI3F
Rising Edge Detector Flag.
This bit is set by hardware when a rising edge oc-
curs on the pin assigned to EI3. It is cleared by
software. When EI3F is set an interrupt is generat-
ed if EI3ITE=1 and the I bit in the CC register = 0.
0: No rising edge detected on EI3
1: Rising edge detected on EI3
Bit 3:0 = EI0ITE, EI1ITE, EI2ITE, EI3ITE
Interrupt
Enable Bits.
These bits are set and cleared by software.
0: Interrupt disabled
1: Interrupt enabled
70
EI4F
EI4ITE
SMS
-
POC0
70
EI0F
EI1F
EI2F
EI3F
EI0ITE
EI1ITE
EI2ITE
EI3ITE