参数资料
| 型号： | ST78C36CJ44-F |
| 厂商： | Exar Corporation |
| 文件页数： | 4/27页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B 44PLCC |
| 标准包装： | 27 |
| 特点： | * |
| FIFO's： | 16 字节 |
| 规程： | 打印机 |
| 电源电压： | 5V |
| 带并行端口： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
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ST78C36/36A
12
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
REV. 5.1.0
4.4.2
ECP REVERSE MODE (PDIR = 1)
PD[7:0] data and BUSY are latched into the FIFO and tag bit respectively at the trailing edge of -AUTOFD if
FIFO-F = 0. Timing is generated by controller logic that handshakes -ACK (peripheral) with -AUTOFD
(controller).
4.5
EPP MODE
This is ECR mode 100.
In this bi-directional mode, I/O writes will latch host output data at the trailing edge of -IOW, and peripheral
input data will be latched at the trailing edge of -SLCTIN or -AUTOFD. PDIR, and -STROBE are driven by the
state of -IOW (DCR bits 5 and 0 must be set low); -AUTOFD, INIT, and -SLCTIN are totem-pole.
EPP mode allows buffered access between the PC bus and the peripheral with timing provided by the
peripheral via BUSY handshake into IOCHRDY. I/O cycles with address 003 - 007 will immediately drive
IOCHRDY low. -STROBE will go low and PD[7:0] is allowed to change (write cycles) after BUSY has been low
for at least 60n second. (this delay may have elapsed prior to cycle initiation), immediately followed by a low
driven on -SLCTIN for address 003 or -AUTOFD (DATASTB*) for address 004 - 007 (read and write cycles).
When BUSY returns high for a minimum of 60n second, IOCHRDY and the active strobe will be driven high -
allowing the host to complete the I/O transaction.
To prevent a system stall, a 10 msecond TimeOut aborts the cycle if it expires before BUSY returns high. This
TimeOut also sets bit 0 of DCR, which is cleared by disabling EPP mode or writing a high to DCR bit 0.
4.6
TST MODE
This is ECR mode 110.
This mode allows data to be transferred (read or write in any direction) between the FIFO and host at address
400 or DMA without activating the control interface (no data is transferred to/from the peripheral). PDIR is
driven by DIR (can only be set in ECR mode 001); -AUTOFD, INIT, and -SLCTIN are totem-pole.
Performing I/O cycles in this mode allows software to test for the value of FIFOThreshold (FT) for both output
and input directions.
4.7
CFG MODE
This is ECR mode 111.
This mode enables I/O access to the configuration registers CONF-A and CONF-B and disables I/O access to
the FIFO.
4.7.1
IRQ
The module has four sources of interrupt which may be directed to -IRQ5, -IRQ7, -IRQ9 (see CONF-B) or
externally jumpered.
1.
When DCR bit 4 (AIE) is high and -ACK is low the interrupt is active.
2.
When ECP mode is active, if ECR bit 4 is low when ERROR transitions low or ECR bit 4 transitions low
when -Fault is low an interrupt pulse of at least 200n seconds will be generated.
3.
In FIFO modes (PPF, ECP, or TST) with ECR bit 3 (DMA) low, an interrupt pulse of at least 200n seconds
will be generated when ECR bit 2 (SI) is set low if there are at least 8 empty bytes in the FIFO and PDIR
= 0 or there are at least 8 filled bytes in the FIFO and PDIR = 1. This interrupt will automatically disable
itself by setting ECR bit 2 high.
4.
In FIFO modes (PPF, ECP, or TST) with (DMA request enabled), an interrupt pulse of at least 200n
seconds will be generated when TC is received if PD-ACK is low.
This interrupt will automatically disable itself and the DMA request by setting ECR bit 2 high.
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