参数资料
| 型号： | ST78C36CJ44-F |
| 厂商： | Exar Corporation |
| 文件页数： | 9/27页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B 44PLCC |
| 标准包装： | 27 |
| 特点： | * |
| FIFO's： | 16 字节 |
| 规程： | 打印机 |
| 电源电压： | 5V |
| 带并行端口： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
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TABLE 9: “ECP MODE” SIGNAL DESCRIPTION
SIGNAL NAME SIGNAL TYPE ECP MODE NAME
DESCRIPTION
-STROBE
O
HostClk
Used with PeriphAck to transfer data or address information in the for-
ward direction.
-AUTOFD
O
HostAck
Provides Command / Data status in the forward direction. Used with
PeriphClk to transfer data in the reverse direction.
-SLCTIN
O
1284Active
Set high when host is in a 1284 transfer mode.
INIT
O
-ReverseReq
Driven low to put the channel in reverse direction.
-ACK
I
PeriphClk
Used with HostAck to transfer data in the reverse direction.
BUSY
I
PeriphAck
Used with HostClk to transfer data or address information in the forward
direction. Provides Command / Data status in the reverse direction.
PE
I
-AckReverse
Driven low to acknowledge ReverseRequest.
SLCT
I
Xflag
Extensibility flag.
-ERROR
I
-PeriphReq
Set low by peripheral to indicate that reverse dat is available.
PD0-PD7
I/O
D0-D7
Bi-directional data lines.
ST78C36/36A
17
REV. 5.1.0
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
5.3
ECP Mode Forward Data and Command Transfer Cycle
■ Host places data on the data lines and indicates a data cycle by setting HostAck high.
■ Host asserts HostClk low to indicate valid data.
■ Peripheral acknowledge host by setting PeriphAck high.
■ Host sets HostClk high. This is the edge that should be used to clock the data in to the peripheral.
■ Peripheral sets PeriphAck low to indicate that it is ready for the next byte.
■ The cycle repeats, but this time it is command cycle because HostAck is low.
5.4
ECP Mode Reverse Data and Command Transfer Cycle
■ The Host requests a reverse channel transfer by setting -ReverseReq low.
■ The peripheral signals that it is okay to proceed by setting -AckReverse low.
■ The peripheral places data on the data lines and indicates a data cycle by setting PeriphAck high.
■ Peripheral asserts PeriphClk low to indicate valid data.
■ Host acknowledges by setting HostAck high.
■ Peripheral sets PeriphClk high. This is the edge that should be used to clock the data in to the host.
■ Host sets HostAck low to indicate that it is ready for the next byte.
■ The cycle repeats, but this time it is a Command cycle because PeriphAck is low.
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