![](http://datasheet.mmic.net.cn/120000/ST7FL34F2MCE_datasheet_3576790/ST7FL34F2MCE_128.png)
On-chip peripherals
ST7L34, ST7L35, ST7L38, ST7L39
Doc ID 11928 Rev 7
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
Procedure
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Select the M bit to define the word length.
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Select the desired baud rate using the SCIBRR and the SCIETPR registers.
●
Set the TE bit to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones (idle
line) as first transmission.
●
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1.
An access to the SCISR register
2.
A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
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The TDR register is empty
●
The data transfer is beginning
●
The next data can be written in the SCIDR register without overwriting the previous
data
This flag generates an interrupt if the TIE bit is set and the I[|1:0] bits are cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a character transmission is complete (after the stop bit) the TC bit is set and an
interrupt is generated if the TCIE is set and the I[1:0] bits are cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1.
An access to the SCISR register
2.
A write to the SCIDR register
Note:
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break character
As long as the SBK bit is set, the SCI sends break characters to the TDO pin. After clearing
this bit by software, the SCI inserts a logic 1 bit at the end of the last break character to
guarantee the recognition of the start bit of the next character.
Idle line
Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive
‘1’s (idle line) before the first character.