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参数资料
| 型号： | ST7SCR |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER |
| 中文描述： | 8位低功耗，全速USB微控制器与16K的闪存，768内存，智能卡的I /楼，计时器 |
| 文件页数： | 47/102页 |
| 文件大小： | 1413K |
| 代理商： | ST7SCR |
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ST7SCR
47/102
USB INTERFACE
(Cont’d)
INTERRUPT MASK REGISTER (USBIMR)
Read/Write
Reset Value: 0000 0000 (00h)
These bits are mask bits for all the interrupt condi-
tion bits included in the USBISTR register. When-
ever one of the USBIMR bits is set, if the corre-
sponding USBISTR bit is set, and the I- bit in the
CC register is cleared, an interrupt request is gen-
erated. For an explanation of each bit, please refer
to the description of the USBISTR register.
CONTROL REGISTER (USBCTLR)
Read/Write
Reset value: 0000 0110 (06h)
Bit 7 =
RSM
Resume Detected
This bit shows when a resume sequence has start-
ed on the USB port, requesting the USB interface
to wake-up from suspend state. It can be used to
determine the cause of an ESUSP event.
0: No resume sequence detected on USB
1: Resume sequence detected on USB
Bit 6 =
USB_RST
USB
Reset detected
.
This bit shows that a reset sequence has started
on the USB. It can be used to determine the cause
of an ESUSP event (Reset sequence).
0: No reset sequence detected on USB
1: Reset sequence detected on USB
Bits [5:4] = Reserved, forced by hardware to 0.
Bit 3 =
RESUME
Resume
.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
Bit 2 =
PDWN
Power down
.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note:
After turning on the voltage regulator, soft-
ware should allow at least 3 μs for stabilisation of
the power supply before using the USB interface.
Bit 1 =
FSUSP
Force suspend mode
.
This bit is set by software to enter Suspend mode.
The ST7 should also be put in Halt mode to reduce
power consumption.
0: Suspend mode inactive
1: Suspend mode active
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
Bit 0 =
FRES
Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
7
0
CTRM
0
SOVR
M
ERRM
SUSP
M
ESUSP
M
RESET
M
SOFM
7
0
RSM
USB_
RST
0
0
RESU
ME
PDWN
FSUSP
FRES
1
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