参数资料
型号: ST8024CTR
厂商: 意法半导体
英文描述: Smartcard interface
中文描述: 智能卡接口
文件页数: 14/30页
文件大小: 550K
代理商: ST8024CTR
Functional description
ST8024
14/30
5
Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
5.1
Power supply
The supply pins for the IC are V
DD
and GND. V
DD
should be in the range of 2.7 to 6.5 V. All
signals interfacing with the system controller are referred to V
DD
, therefore V
DD
should also
supply the system controller. All card reader contacts remain inactive during power-on or
power-off.
The internal circuits are maintained in the reset state until V
DD
reaches V
th2
+V
hys2
and for
the duration of the internal Power-on reset pulse, t
W
(see
Figure 4.
). When V
DD
falls below
V
th2
, an automatic deactivation of the contacts is performed.
A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (V
CC
). The
DC/DC converter should be supplied separately by V
DDP
and PGND. Due to the possibility
of large transient currents, the two 100 nF capacitors of the DC/DC converter should be
located as near as possible to the IC and have an ESR less than 100 m
.
The DC/DC converter functions as a voltage doubler or a voltage follower according to the
respective values of V
CC
and V
DDP
(both have thresholds with a hysteresis of 100 mV).
The DC/DC converter function changes as follows:
V
CC
= 5 V and V
DDP
> 5.8 V; voltage follower
V
CC
= 5 V and V
DDP
< 5.7 V; voltage doubler
V
CC
= 3 V and V
DDP
> 4.1 V; voltage follower
V
CC
= 3 V and V
DDP
< 4.0 V; voltage doubler.
Supply voltages V
DD
and V
DDP
may be applied to the IC in any sequence.
After powering the device, OFF remains LOW until CMDVCC is set HIGH.
During power off, OFF falls LOW when V
DD
is below the falling threshold voltage.
5.2
Voltage supervisor
5.2.1
Without external divider on pin PORADJ
The voltage supervisor surveys the V
DD
supply. A defined reset pulse of approximately 8ms
(t
W
) is used internally to keep the IC inactive during power-on or power-off of the V
DD
supply
(see
Figure 4.
).
As long as V
DD
is less than V
th2
+ V
hys2
, the IC remains inactive whatever the levels on the
command lines. This state also lasts for the duration of t
W
after V
DD
has reached a level
higher than V
th2
+ V
hys2
. When V
DD
falls below V
th2
, a deactivation sequence of the
contacts is performed.
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