- 您现在的位置：买卖IC网 > PDF目录98146 > ST90158M9Q6 (STMICROELECTRONICS) 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 PDF资料下载
参数资料
| 型号： | ST90158M9Q6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 163/199页 |
| 文件大小： | 3266K |
| 代理商： | ST90158M9Q6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页当前第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
66/199
ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
5.6 DMA REGISTERS
As each peripheral DMA channel has its own spe-
cific control registers, the following register list
should be considered as a general example. The
names and register bit allocations shown here
may be different from those found in the peripheral
chapters.
DMA COUNTER POINTER REGISTER (DCPR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 7:1 = C[7:1]:
DMA Transaction Counter Point-
er.
Software should write the pointer to the DMA
Transaction Counter in these bits.
Bit 0 = RM:
Register File/Memory Selector.
This bit is set and cleared by software.
0: DMA transactions are with memory (see also
DAPR.DP)
1: DMA transactions are with the Register File
GENERIC EXTERNAL PERIPHERAL INTER-
RUPT AND DMA CONTROL (IDCR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 5 = IP:
Interrupt Pending.
This bit is set by hardware when the Trigger Event
occurs. It is cleared by hardware when the request
is acknowledged. It can be set/cleared by software
in order to generate/cancel a pending request.
0: No interrupt pending
1: Interrupt pending
Bit 4 = DM:
DMA Request Mask.
This bit is set and cleared by software. It is also
cleared when the transaction counter reaches
zero (unless SWAP mode is active).
0: No DMA request is generated when IP is set.
1: DMA request is generated when IP is set
Bit 3 = IM:
End of block Interrupt Mask.
This bit is set and cleared by software.
0: No End of block interrupt request is generated
when IP is set
1: End of Block interrupt is generated when IP is
set. DMA requests depend on the DM bit value
as shown in the table below.
Bit 2:0 = PRL[2:0]:
Source Priority Level.
These bits are set and cleared by software. Refer
to Section 5.2 DMA PRIORITY LEVELS for a de-
scription of priority levels.
DMA ADDRESS POINTER REGISTER (DAPR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 7:1 = A[7:1]:
DMA Address Register(s) Pointer
Software should write the pointer to the DMA Ad-
dress Register(s) in these bits.
Bit 0 = PS:
Memory Segment Pointer Selector:
This bit is set and cleared by software. It is only
meaningful if DAPR.RM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
70
C7
C6
C5
C4
C3
C2
C1
RM
70
IP
DM
IM
PRL2 PRL1 PRL0
DM IM Meaning
10
A DMA request generated without End of Block
interrupt when IP=1
11
A DMA request generated with End of Block in-
terrupt when IP=1
00
No End of block interrupt or DMA request is
generated when IP=1
01
An End of block Interrupt is generated without
associated DMA request (not used)
PRL2 PRL1 PRL0 Source Priority Level
0000 Highest
0011
0102
0113
1004
1015
1106
1117 Lowest
70
A7
A6
A5
A4
A3
A2
A1
PS
9
相关PDF资料 |
PDF描述 |
|---|---|
| ST9020B6/XX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| ST9027B6/XX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| ST9036C6 | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC68 |
| ST9036C1 | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC68 |
| ST9040B6 | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST90158M9T1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90158M9T6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST90158P9C6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST90158-ST90135 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST9016 | 制造商:SEMTECH_ELEC 制造商全称:SEMTECH ELECTRONICS LTD. 功能描述:NPN Silicon Epitaxial Planar Transistor |
发布紧急采购，3分钟左右您将得到回复。