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参数资料
| 型号： | ST95P08B3TR |
| 厂商： | 意法半导体 |
| 英文描述： | MOSFET, P, SOT-23; Transistor type:MOSFET; Current, Id cont:3A; Resistance, Rds on:0.05R; Voltage, Vgs Rds on measurement:4.5V; Case style:SOT-23 (TO-236); Current, Id max:3.0A; Current, Idm pulse:12A; Marking, SMD:M5; Pins, No. RoHS Compliant: Yes |
| 中文描述： | 8千位的SPI EEPROM，带有正时钟选通 |
| 文件页数： | 4/16页 |
| 文件大小： | 119K |
| 代理商： | ST95P08B3TR |
POWER ON STATE
After a Power up the ST95P08 is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
– BP1 and BP0 are unchanged (non-volatile bits).
DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protected against noise, see Table
3.
– Non valid S and HOLD transitions are not taken
into account.
– S must come high at the proper clock count in
order to start a non-volatile write cycle (in the
memory array or in the cycle status register). The
Chip Select S must rise during the clock pulse
following the introduction of a multiple of 8 bits.
– Access to the memory array during non-volatile
programming cycle is cancelled and the chip is
automatically deselected; however, the pro-
gramming cycle continues.
– After either of the following operations (WREN,
WRDI, RDSR) is completed, the chip enters a
wait state and waits for a deselect.
– The write enable latch is reset upon power-up.
– The write enable latch is reset when W is brought
low.
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all "1’s" or FFh).
The block protect bits are initialized to 00.
C
D
AI01432
S
Q
2
1
3456789 10 11 12 13 14 15
HIGH IMPEDANCE
INSTRUCTION
STATUS REG.
0
Figure 13. WRSR: Write Status Register Sequence
12/16
ST95P08
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相关代理商/技术参数 |
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| ST95P08B6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:SPI Serial EEPROM |
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| ST95P08M3 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:SPI Serial EEPROM |
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