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| 型号： | STAR250BK7 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | 250K Pixel Radiation Hard CMOS Image Sensor |
| 中文描述： | 25万像素辐射硬CMOS图像传感器 |
| 文件页数： | 8/24页 |
| 文件大小： | 441K |
| 代理商： | STAR250BK7 |
CYIS1SM0250-AA
Document Number: 38-05713 Rev. *B
Page 16 of 24
3
RESET
Resets row indicated by left/right shift register.
high active (1= reset row).
Apply pulse pattern - see sensor timing diagram.
4
SELECT
Selects row indicated by left/right shift register.
high active (1=select row).
Apply 5 V DC for normal operation.
5
L/R
Use left or right shift register for SELECT and RESET.
1 = left / 0 = right - see sensor timing diagram.
6
A0
Start address for X- and Y- pointers (LSB).
7
A1
Start address for X- and Y- pointers.
8
A2
Start address for X- and Y- pointers.
13
A3
Start address for X- and Y- pointers.
14
A4
Start address for X- and Y- pointers.
15
A5
Start address for X- and Y- pointers.
16
A6
Start address for X- and Y- pointers.
17
A7
Start address for X- and Y- pointers.
18
A8
Start address for X- and Y- pointers (MSB).
19
LD_Y
Latch address (A0…A8) to Y start register (0 = track, 1 = hold).
20
LD_X
Latch address (A0…A8) to X start register(0 = track, 1 = hold).
21
CLK_YL
Clock YL shift register (shifts on falling edge).
22
SYNC_YL
Sets YL shift register to location preloaded in Y start register.
Low active (0=sync).
Apply SYNC_YL when CLK_YL is high.
24
CLK_X
Clock X shift register (output valid & s when CLK_X is low).
25
SYNC_X
Sets X shift register to location preloaded in X start register.
Low active (0=sync).
Apply SYNC_X when CLK_X is high.
After SYNC_X, apply falling edge on CLK_X, and rising edge on CLK_X.
27
CLK_YR
Clock YR shift register (shifts on falling edge).
28
SYNC_YR
Sets YR shift register to location preloaded in Y start register.
Low active (0=sync).
Apply SYNC_YR when CLK_YR is high.
36
CAL
Initialize output amplifier.
Output amplifier will output BLACKREF in unity gain mode when CAL is high (1).
Apply pulse pattern (one pulse per frame) - see sensor timing diagram.
37
G0
Select output amplifier gain value: G0 = LSB; G1 = MSB.
00 = unity gain; 01 = x2; 10= x4; 11=x8.
38
G1
idem.
71
CLK_ADC
ADC clock.
ADC converts on falling edge.
75
BITINVERT
1 = invert output bits.
0 = no inversion of output bits.
Table 10. Digital Input Signals (continued)
Pin
Pin Name
Pin Description
[+] Feedback
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| STAR-9001 | 制造商:Stancor 功能描述:Plug-In Adapter Single-OUT 5V 1A |
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| STAR-9002-9 | 制造商:Stancor 功能描述: |
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