参数资料
型号: STCL1120YBFCWY5
厂商: STMICROELECTRONICS
元件分类: 时钟产生/分配
英文描述: 12 MHz, OTHER CLOCK GENERATOR, PDSO5
封装: ROHS COMPLIANT, SOT-23, 5 PIN
文件页数: 14/17页
文件大小: 147K
代理商: STCL1120YBFCWY5
Typical application circuit
STCL1100 STCL1120 STCL1160
6/17
2
Typical application circuit
Figure 2.
Microprocessor (MCU, microcontroller unit) clock example
- replacement of a crystal or ceramic resonator
1.
For reliable operation and to further improve immunity to harsh environment, the minimum 0.1 F decoupling capacitor is
recommended to be placed as close as possible to the VCC and GND pins of the oscillator device. The whole oscillator
block should then be placed near the microprocessor clock input.
2.
To minimize standby current, no internal pull-up resistor to VCC is implemented on the CE input, thus the input level must
be permanently defined by the controlling signal. If the chip enable feature is not used, in active mode connect the CE pin
to VCC. In applications utilizing standby mode and where the CE pin is connected to the controlling I/O port of the clocked
microprocessor, for successful startup of the microprocessor at power-on, initial logic high level needs to be secured on the
CE pin to provide clock already during the power-on reset until the microprocessor program starts and the controlling I/O
port takes over the CE control.
AI12657d
STCL1xx0
1
5
3
4
2
CE (2)
VCC
NC
FOUT
GND
MCU
I/O
Xtal1
(OSC1,
OSCin)
Xtal2
(OSC2,
OSCout)
NC
VCC
5 V
GND
0.1 F(1)
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