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参数资料
| 型号： | STK11C68-5K55M |
| 元件分类： | SRAM |
| 英文描述： | 8K X 8 NON-VOLATILE SRAM, 55 ns, CDIP28 |
| 封装： | 0.300 INCH, CERAMIC, DIP-28 |
| 文件页数： | 11/12页 |
| 文件大小： | 280K |
| 代理商： | STK11C68-5K55M |
STK11C68
March 2006
8
Document Control # ML0007 rev 0.2
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the t
RECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL
operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC < VRESET), an internal RECALL request will be
latched. When V
CC once again exceeds the sense
voltage of V
SWITCH, a RECALL cycle will automatically
be initiated and will take t
RESTORE to complete.
If the STK11C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC or between E and system VCC.
HARDWARE PROTECT
The STK11C68 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When V
CC
< V
SWITCH,
software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
CC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, V
CC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE
cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the Vcc level; and 7) I/O loading.
Figure 2: ICC (max) Reads
0
20
40
60
80
100
50
100
150
200
Cycle Time (ns)
TTL
CMOS
A
v
er
age
Act
ive
C
u
rr
ent
(
m
A)
Figure 3: ICC (max) Writes
0
20
40
60
80
100
50
100
150
200
Cycle Time (ns)
TTL
CMOS
A
v
er
age
Act
ive
C
u
rr
ent
(
m
A)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| STK11C68-5L30M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (EEPROM Based) |
| STK11C68-5L35M | 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| STK11C68-5L45M | 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| STK11C68-5L55M | 功能描述:NVRAM 8Kbx8 4.5-5.5V Softstore RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| STK11C68-5P25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (EEPROM Based) |
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