参数资料
型号: STK17CA8-W45I
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDIP40
封装: 0.600 INCH, DIP-40
文件页数: 7/22页
文件大小: 579K
代理商: STK17CA8-W45I
STK17CA8
June 2003
15
Document Control # ML0023 rev 0.2
counter load register. Counting begins on power up
and restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to 1. The counter
is compared to the terminal value of 0. If the counter
reaches this value, it causes an internal flag and an
optional interrupt output. The user can prevent the
timeout interrupt by setting WDS bit to 1 prior to the
counter reaching 0. This causes the counter to be
reloaded with the watchdog timeout value and to be
restarted. As long as the user sets the WDS bit prior
to the counter reaching the terminal value, the inter-
rupt and flag never occurs.
New timeout values can be written by setting the
watchdog write bit to 0. When the WDW is 0 (from
the previous operation), new writes to the watchdog
timeout value bits D5-D0 allow the timeout value to
be modified. When WDW is a 1, then writes to bits
D5-D0 will be ignored. The WDW function allows a
user to set the WDS bit without concern that the
watchdog timer value will be modified. A logical dia-
gram of the watchdog timer is shown below. Note
that setting the watchdog timeout value to 0 would
be otherwise meaningless and therefore disables
the watchdog function.
The output of the watchdog timer is a flag bit WDF
that is set if the watchdog is allowed to timeout. The
flag is set upon a watchdog timeout and cleared
when the Flags/Control register is read by the user.
The user can also enable an optional interrupt
source to drive the INT pin if the watchdog timeout
occurs.
POWER MONITOR
The STK17CA8 provides a power management
scheme with power-fail interrupt capability. It also
controls the internal switch to backup power for the
clock and protects the memory from low-Vcc
access. The power monitor is based on an internal
band-gap reference circuit that compares the Vcc
voltage to various thresholds.
As descibed in the AutoStore section previously,
when Vswitch is reached as Vcc decays from power
loss, a data store operation is initiated from SRAM
to the nonvolatile elements, securing the last SRAM
data state. Power is also switched from Vccx to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source no data
may be read or written and the clock functions are
not available to the user. The clock continues to
operate in the background. Updated clock data is
available to the user 10 msec after Vcc has been
restored to the device.
INTERRUPTS
The STK17CA8 provides three potential interrupt
sources. They include the watchdog timer, the
power monitor, and the clock/calendar alarm. Each
can be individually enabled and assigned to drive
the INT pin. In addition, each has an associated flag
bit that the host processor can use to determine the
cause of the interrupt.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when
an interrupt occurs. A functional diagram of the
interrupt logic is shown below.
The three interrupts each have a source and an
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
Figure 5. Watchdog Timer Block Diagram
Figure 6. Interrupt Block Diagram
相关PDF资料
PDF描述
STK17T88-RF45TR PROGRAMMABLE TIMER, PDSO48
STK17T88-RF45 PROGRAMMABLE TIMER, PDSO48
STK17T88-RF25ITR PROGRAMMABLE TIMER, PDSO48
STK17TA8-R25I REAL TIME CLOCK, PDSO48
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