参数资料
型号: STK17CA8-W45I
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDIP40
封装: 0.600 INCH, DIP-40
文件页数: 8/22页
文件大小: 579K
代理商: STK17CA8-W45I
STK17CA8
June 2003
16
Document Control # ML0023 rev 0.2
output. Only one source is necessary to drive the
pin. The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to
0 when the register is read. The cycle must be a
complete read cycle (WE high); otherwise the flags
will not be cleared. The power monitor has two pro-
grammable settings that are explained in the power
monitor section.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
According to the programming selections, the pin
can be driven in the backup mode for an alarm inter-
rupt. In addition, the pin can be an active low (open-
drain) or an active high (push-pull) driver. If pro-
grammed for operation during backup mode, it can
only be active low. Lastly, the pin can provide a one-
shot function so that the active condition is a pulse
or a level condition. In one-shot mode, the pulse
width is internally fixed at approximately 200 ms.
This mode is intended to reset a host microcontrol-
ler. In level mode, the pin goes to its active polarity
until the Flags/Control register is read by the user.
This mode is intended to be used as an interrupt to
a host microcontroller. The control bits are summa-
rized as follows:
Watchdog Interrupt Enable - WIE. When set to 1,
the watchdog timer drives the INT pin as well as an
internal flag when a watchdog timeout occurs.
WhenWIE is set to 0, the watchdog timer affects
only the internal flag.
Alarm Interrupt Enable - AIE. When set to 1, the
alarm match drives the INT pin as well as an internal
fla. When set to 0, the alarm match only affects to
internal flag.
Power Fail Interrupt Enable - PFE. When set to 1,
the power fail monitor drives the pin as well as an
internal flag. When set to 0, the power fail monitor
affects only the internal flag.
Alarm Battery-backup Enable - ABE. When set to 1,
the clock alarm interrupt (as controlled by AIE) will
function even in battery backup mode. When set to
0, the alarm will occur only when Vcc>Vswitch. AIE
should only be set when the INT pin is programmed
for active low operation. In addition, it only functions
with the clock alarm, not the watchdog. If enabled,
the power monitor will drive the interrupt during all
normal Vcc conditions regardless of the ABE bit.
The application for ABE is intended for power con-
trol, where the system powers up at a predeter-
mined time. Depending on the application, it may
require dedicating the INT pin to this function.
High/Low - H/L. When set to a 1, the INT pin is
active high and the driver mode is push-pull. The
INT pin can drive high only when Vcc>Vswitch.
When set to a 0, the INT pin is active low and the
drive mode is open-drain. Active low (open drain) is
operational even in battery backup mode.
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, as external host can read the Flags/Control reg-
ister to determine the cause. Remember that all
flags will be cleared when the register is read. If the
INT pin is programmed for Level mode, then the
condition will clear and the INT pin will return to its
inactive state. If the pin is programmed for Pulse
mode, then reading the flag also will clear the flag
and the pin. The pulse will not complete its specified
duration if the Flags/Control register is read. If the
INT pin is used as a host reset, then the Flags/Con-
trol register cannot be read during a reset.
During a power-on reset with no battery, the inter-
rupt register is automatically loaded with the value
24h. This causes power-fail interrupt to be enabled
with an active-low pulse.
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