参数资料
型号: STK17T88-RF25ITR
元件分类: 时钟/数据恢复及定时提取
英文描述: PROGRAMMABLE TIMER, PDSO48
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SSOP-48
文件页数: 11/29页
文件大小: 535K
代理商: STK17T88-RF25ITR
19
STK17T88
Jan, 2008
Document Control #ML0024 Rev 2.0
INTERRUPT REGISTER
Watchdog Interrupt Enable (WIE). When set to 1,
the watchdog timer drives the INT pin when a watch-
dog time-out occurs. When WIE is set to 0, the
watchdog time-out only sets the WDF flag bit.
Alarm Interrupt Enable (AIE). When set to 1, the INT
pin is driven when an alarm match occurs. When set
to 0, the alarm match only sets the AF flag bit.
Power Fail Interrupt Enable (PFE). When set to 1,
the INT pin is driven by a power fail signal from the
power monitor. When set to 0, only the PF flag is set.
High/Low (H/L). When set to a 1, the INT pin is
active high and the driver mode is push-pull. The
INT pin can drive high only when VCC>VSWITCH.
When set to a 0, the INT pin is active low and the
drive mode is open-drain. The active low (open
drain) output is maintained even when power is lost.
Pulse/Level (P/L). When set to a 1, the INT pin is
driven for approximately 200 ms when the interrupt
occurs. The pulse is reset when the Flags register is
read. When P/L is set to a 0, the INT pin is driven
high or low (determined by H/L) until the Flags regis-
ter is read.
The Interrupt register is loaded with the default value
00h at the factory. The user should configure the
Interrupt register to the value desired for their
desired mode of operation. Once configured, the
value is retained during power failures.
FLAGS REGISTER
The Flags register has three flag bits: WDF, AF, and
PF. These flags are set by the watchdog time-out,
alarm match, or power fail monitor respectively. The
processor can either poll this register or enable the
interrupts to be informed when a flag is set. The
flags are automatically reset once the register is
read.
The Flags register is automatically loaded with the
value 00h on power up (with the exception of the
OSCF bit).
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