参数资料
型号: STK17T88-RF25ITR
元件分类: 时钟/数据恢复及定时提取
英文描述: PROGRAMMABLE TIMER, PDSO48
封装: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SSOP-48
文件页数: 9/29页
文件大小: 535K
代理商: STK17T88-RF25ITR
17
STK17T88
Jan, 2008
Document Control #ML0024 Rev 2.0
The STK17T88 has the ability to detect oscillator
failure due to loss of backup power. The failure is
recorded by the OSCF (Oscillator Failed bit) of the
Flags register (at address 0x7FF0). When the
device is powered on (VCC goes above VSWITCH)
the OSCEN bit is checked for “enabled” status. If the
OSCEN bit is enabled and the oscillator is not active
within 5 ms, the OSCF bit is set. The user should
check for this condition and then write a 0 to clear
the flag. When the OSCF flag bit, the real time clock
registers are reset to the “Base Time” (see the sec-
last written to the real time clock registers.
The value of OSCF should be reset to 0 when the
real time clock registers are written for the first time.
This will initialize the state of this bit since it may
have become set when the system was first pow-
ered on.
To reset OSCF, set the write bit “W” (in the Flags
register at 0x7FF0) to a “1” to enable writes to the
Flags register. Write a “0” to the OSCF bit and then
reset the write bit to “0” to disable writes.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal
specified (usually 35 ppm at 25 C). This error could
equate to 1.53 minutes gain or loss per month. The
STK17T88 employs a calibration circuit that can
improve the accuracy to +1/-2 ppm at 25 C. The cal-
ibration circuit adds or subtracts counts from the
oscillator divider circuit.
The number of time pulses added or subtracted
depends upon the value loaded into the five calibra-
tion bits found in Calibration register (at 0x7FF8).
Adding counts speeds the clock up; subtracting
counts slows the clock down. The Calibration bits
occupy the five lower order bits of the register.
These bits can be set to represent any value
between 0 and 31 in binary form. Bit D5 is a Sign bit,
where a “1” indicates positive calibration and a “0”
indicates negative calibration. Calibration occurs
during a 64 minute period. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and
so on. Therefore each calibration step has the effect
of adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the Calibration register.
The calibration register value is determined during
system test by setting the CAL bit in the Flags regis-
ter (at 0x7FF0) to 1. This causes the INT pin to tog-
gle at a nominal 512 Hz. This frequency can be
measured with a frequency counter. Any deviation
measured from the 512 Hz will indicate the degree
and direction of the required correction. For exam-
ple, a reading of 512.01024 Hz would indicate a +20
ppm error, requiring a -10 (001010) to be loaded into
the Calibration register. Note that setting or chang-
ing the calibration register does not affect the fre-
quency test output frequency.
To set or clear CAL, set the write bit “W” (in the Flags
register at 0x7FF0) to a “1” to enable writes to the
Flags register. Write a value to CAL and then reset
the write bit to “0” to disable writes.
The default Calibration register value from the fac-
tory is 00h. The user calibration value loaded is
retained during a power loss.
ALARM
The alarm function compares a user-programmed
alarm time/date (stored in registers 0x7FF1-5) with
the real time clock time-of-day/date values. When a
match occurs, the alarm flag (AF) is set and an inter-
rupt is generated if the alarm interrupt is enabled.
The alarm flag is automatically reset when the Flags
register is read.
Each of the alarm registers has a match bit as its
MSB. Setting the match bit to a 1 disables this alarm
register from the alarm comparison. When the
match bit is 0, the alarm register is compared with
the equivalent real time clock register. Using the
match bits, an alarm can occur as specifically as one
particular second on one day of the month or as fre-
quently as once per minute.
Note: The product requires the match bit for sec-
onds (0x7FF2, bit D7) be set to 0 for proper oper-
ation of the Alarm Flag and Interrupt.
The alarm value should be initialized on power-up by
software since the alarm registers are not non-
volatile.
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