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参数资料
型号： STM32F103ZDT6XXX
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP144
封装： 20 X 20 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件页数： 26/122页
文件大小： 1599K
代理商： STM32F103ZDT6XXX
STM32F103xC, STM32F103xD, STM32F103xE
Revision history
Doc ID 14611 Rev 6
121/122
21-Jul-2009
6
Figure 1: STM32F103xC, STM32F103xD and STM32F103xE
performance line block diagram updated.
Note 5 updated and Note 4 added in Table 5: High-density
STM32F103xx pin definitions.
VRERINT and TCoeff added to Table 13: Embedded internal reference
voltage.
Table 16: Maximum current consumption in Sleep mode, code running
from Flash or RAM modified.
fHSE_ext min modified in Table 21: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator
characteristics and Table 24: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables.
Note 1 modified below Figure 21: Typical application with an 8 MHz
crystal. Table 25: HSI oscillator characteristics modified. Conditions
removed from Table 27: Low-power mode wakeup timings.
Jitter added to Table 28: PLL characteristics.
Figure 42: Recommended NRST pin protection modified.
In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
timings: th(BL_NOE) and th(A_NOE) modified.
In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings: th(A_NWE) and th(Data_NWE) modified.
In Table 33: Asynchronous multiplexed PSRAM/NOR read timings:
th(AD_NADV) and th(A_NOE) modified.
In Table 34: Asynchronous multiplexed PSRAM/NOR write timings:
th(A_NWE) modified.
In Table 35: Synchronous multiplexed NOR/PSRAM read timings:
th(CLKH-NWAITV) modified.
In Table 40: Switching characteristics for NAND Flash read and write
cycles: th(NOE-D) modified.
Table 52: SPI characteristics modified. Values added to Table 53: I2S
characteristics and Table 54: SD / MMC characteristics.
CADC and RAIN parameters modified in Table 58: ADC characteristics.
RAIN max values modified in Table 59: RAIN max for fADC = 14 MHz.
Table 62: DAC characteristics modified. Figure 56: 12-bit buffered /non-
buffered DAC added.
Figure 59: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline and Table 65: LFBGA100 - 10 x 10 mm low profile fine
pitch ball grid array package mechanical data updated.
Table 72.
Document revision history
Date
Revision
Changes
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相关代理商/技术参数
参数描述
STM32F103ZDT7TR 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103ZDT7XXX 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103ZDY6TR 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103ZDY6XXX 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103ZDY7TR 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
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