参数资料
型号: STM32F103ZGH7TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA144
封装: 10 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-144
文件页数: 25/45页
文件大小: 803K
代理商: STM32F103ZGH7TR
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Doc ID 17144 Rev 2
D5 60 94 138
BOOT0
I
BOOT0
C5 61 95 139
PB8
I/O FT
PB8
TIM4_CH3(7) / SDIO_D4
I2C1_SCL/
CAN_RX
B5
62 96 140
PB9
I/O FT
PB9
TIM4_CH4(7) / SDIO_D5
I2C1_SDA /
CAN_TX
A5
-
97 141
PE0
I/O FT
PE0
TIM4_ETR / FSMC_NBL0
A4
-
98 142
PE1
I/O FT
PE1
FSMC_NBL1
E5
63 99 143
VSS_3
SVSS_3
F5
64 100 144
VDD_3
SVDD_3
1.
I = input, O = output, S = supply.
2.
FT = 5 V tolerant.
3.
Function availability depends on the chosen device.
4.
If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5.
PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6.
Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7.
This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
8.
For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144/BGA144
packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate
function I/O and debug configuration section in the STM32F10xxx reference manual.
9.
For devices delivered in LQFP64 packages, the FSMC function is not available.
Table 5.
STM32F103xF and STM32F103xG pin definitions (continued)
Pins
Pin name
Ty
p
e
(1
)
I/
O
l
e
vel
(2)
Main
function(3)
(after reset)
Alternate functions(4)
LFBGA
144
LQ
FP64
LQ
F
P
1
0
LQ
F
P
1
4
Default
Remap
相关PDF资料
PDF描述
STM32F103ZFT7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP144
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